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TM58P05
1 . oS(c)E ROM: 0.5K x 14 |i RAM: 33 x 8 |i iI: 4 A I/O f : 12 -O I/O (c)w(R)E3/4 /-p1/4AE3/4: 8 |i x 1 (TMR) 0 wAAW3/48 |i : 2 -OA_1/2D A_1/2D (TMR ) : : 0 ~A_1/2D (PA 0 : ) Watchdog-p(R)E3/4: |bauWo(c)oRC(R)Au3/4 watchdog Iu(c)PAO20mS; IaiqLI , IwAAW3/4I atchdog*X(c)PAFi2.6SC w Wq_|i & 1/4q_|i _|i-p(R)E3/4: 20 mS (5V) 1 -O RC(R)Au3/4 4 Iu~(R)Au1/4O|: RC(c)M (LS,NS,HS) O 2 Iu3/4@1/4O|@e1/4O| A1/4O| : , u@qA 2.5Va5.5V : uO 79 -O : eo: watchdog-p(R)E3/4*X Port A (PA 3 PA 0 , ~ ) _|i|Vq 1FFH : A_1/2D|Vq 1FEH : CqAAEu: qAN3/4E-P_|iC
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Rev:1.0 Page:1/1
TM58P05
2.}|i(c)wq
PA2 PA3 EXT_CLK RESETB/VP P VSS PB0 PB1 PB2 PB3 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 PA1 PA0 OSC 1 OSC 2 VDD PB7 PB6 PB5 PB4
Package Types :PDIP. PA2 PA3 EXT_CLK RESETB/VP P VSS VSS PB0 PB1 PB2 PB3 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 PA1 PA0 OSC 1 OSC 2 VDD VDD PB7 PB6 PB5 PB4
Package Type : OIC. S
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Rev:1.0 Page:2/2
TM58P05
}|iy-z }|i|WU EXT_CLK PA0 PA3 -0 PB-0 7 RESET B/VPP I/O I I I/O I/O I y-z TMR0 -p1/4AE3/4~(R)EAAeJ} I/O f & ~A_1/2DeJ & eoeJ I/O f & eo (eJ1/4O| ) I/O f tI_|iH & VPP (qA ) eJ 1 2 OSC1 OSC2 VDD VSS I O P P CqA: _|i1/4O| qA : 1/2s{1/4O|
(R)Au3/4eJ (R)Au3/4eX q*1/2eJ |aeJ I: eJ ; O: eX; I/O: Bi-e|V; P: q*1/2
3. |sAx3/4 Name CONFIG (Instruction) SELECT INDF TMR0 PC STATUS $00 $01 $02 $03 D7 D7 A6 D6 D6 Addr Bit 7 Bit 6 LV 1 Bit 5 LV 0 Bit 4 TYPE Bit 3 CPT PSA A3 D3 D3 Bit 2 WDTE PS 2 A2 D2 D2 Bit 1 Bit 0
FOSC FOSC 1 0 PS 1 A1 D1 D1 PS 0 A0 D0 D0
SUR0 EDGE0 A5 D5 D5 A4 D4 D4
FSR I/O Port A I/O Port B WAKE_UP IRQM IRQF
$04 $05 $06 $20 $21 $22 PB7 WDTS INTM PB6 WUE PB5 EIS
TO D4 PB4
PD D3 PA3 PB3 PUH3
Z D2 PA2 PB2 PUH2 EXINTM EXINTF
DC D1 PA1 PB1 PUH1
C D0 PA0 PB0 PUH0 TMR0M TMR0F
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Rev:1.0 Page:3/3
TM58P05
4. tIIi
A_i3/4
uOH|s3/4
EPROM512 *14
{C-p1/4AE3/4 PB7 0 :PB I/O Port PA3 :PA0 uON1/2X3/4
4AiI
Data Bus
TMR0
Option H|s3/4
Status
Acc
FSR
Watchdog/TMR 0 wAAW3/4
ALU and Control Unit
33|r RAM
Watchdog -p(R)E3/4
(R)Au3/4&CqAAEu3/4
Configuration Word
EXT_CLK
Sleep OSC OSC 1 2
RESETB/VP P
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Rev:1.0 Page:4/4
TM58P05
5.
|sAx3/4N TM58P05 |sAx3/4A{C|sAx3/4(c)M1/4AE3/4U|sAx3/4C
5 . 1 {C|sAx3/4 TM58P05 N 2 Iu{C|sAx3/4M , Y@e1/4O|(c)MA1/4O|CIaiqL]m configure word
i3/4U|P1/4O|C |b@e1/4O|U , i1/2M}|P@-Wu| , {C-p 1/4AE3/4|UE[ -p1/4AE3/4iAUCC |bA1/4O|U , TM58P05 \1/2M} 0.5K |sAx3/4o|o|a} , |Ou--jp--iCt~ , 1 CM|OC]aQ 512 -O|rC skip, call, goto uOo|aeCON{C-p1/4AE3/4i uOiAU , (c)IIqL3/4E1/4AE3/4Ui{C
lcall (c)M lgoto uOiNAEFM}1/4O|C
TM58P05 |@-OiXY 0.5K A i 0.5K |sAx3/4 , ]NO 0.5K+M 000h B-OEC ROM c|pI
9 |i{C-p1/4AE3/4C
|pGXY|a}WL 0.5K, |a}*|M NOP uO*|3/4E-P|b|a}
N*|Mi M. |b_|i|Vq|im[@-O 5 -1 (c)O U :
A1/4O| @e1/4O|
000H 000H ... ... Program ... 0FDH
Page 0 0FFH 100H Page 1
1FEH IRQ vector
1FEH 1FFH Reset vector 1FFH Reset vector
I 5 -1 ROM c
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Rev:1.0 Page:5/5
TM58P05
TM58P05u|bA1/4O|NA_1/2D\aC|bO1/4O|U|a} \ , 1/2s1/2XOA@ B|aeAi3/4U(c)Mq-|pI 5.2 (c)OU : ; 1EEH O|sA_|VqC Iai
qL]m configuration wordiJA1/4O|C configuration word|i(c)o 800H, ]t(R)Aui3/4U , WDT
Bit
Symbol Bit1 0 0 1 1 Bit0 0 1 0 1
Description OSC Type LS (Ct ) NS (@etx ) HS (t ) RC Resonance Fre quency 32~200Khz 1~10Mhz 10~20Mhz 31K ~ 6M Hz
1~0
FOSC ~FOSC 1 0
WDTE: Watchdog enable/disable control 2 WDTE 1: WDT enable 0: WDT disable CPT: Code Protect bit ion 3 CPT 1: OFF 0: ON TYPE: Select operat mode ing 4 TYPE LV 1 1 1: Advanced mode 0: General mode LV 0 1 Detect voltage Don't use
6~5
LV1 ~LV0
0 1 0
1 0 0 I 5-2 Configuration Word
1V 2V 4V
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Rev:1.0 Page:6/6
TM58P05
5 . 2 1/4AE3/4U|sAx3/4 1/4AE3/4U|sAx3/4ONMI\aH|s3/4(c)MqIAH3/4/|sAx3/4O|C1/4AE3/4U|sAx3/4jpO(c)T(c)w , |O(R)U3/4U configure word bit4 OM(c)w (@e1/4O|(c)IA1/4O|)C |b@e1/4O|U TM58P05 , N25-OqLbanki3/4U3/4/i|su1/4AE3/4UqIH|s3/4C 3/4]t{C-p1/4AE3/4 MI\aH|s
, -p(R)E3/4 (TMR0 )H|s3/4, AH|s3/4,i3/4UH|s3/4 (BANK), I/OH|s3/4C|~
TM58P05 |3-OUH|s3/4 M}H|s3/4 : (IAR), i3/4UH|s3/4(Select) I/O direction register , (IODIR)C @e1/4O|H|s3/4M|p I5-3(c)OU : RAM_General(Type=0 ) Bank0 00h 01h 02h 03h 04h 05h 06h IAR TMR0 PC STATUS FSR PORTA PORTB General Purpose Register 07 - 0F
9+16=25 General Purpose Register 10 -1F
I5-3 @e1/4O|H|s3/4M
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Rev:1.0 Page:7/7
TM58P05
A. M}H|s3/4OzH|s3/4, |OOHM}Oi3/4UH|s3/4CXYM}H|s3/4 o|ouOeUWOMi(c)Oi3/4UH|s3/4(c)Ou|a}C |]M}H|s3/4Oz1/2uo , IaAuM}H|s3/4- (BSR=00H) NAO|^1/4AE3/4U00h C1/4gM}H|s3/4-|P (c)oNOP uOC B. i3/4UH|s3/4IOi WDT(c)M TMR0 |b1/4AE3/4U|sAx3/4|At@ -OS(c)w|a} , |OqLi C 3/4UuOu]mi|i , ]NO, |Ou1/4gH|s3/4CO[3/4(R)eN*|qLo|aei3/4UuO Qeii3/4U H|s3/4C|pG{C1/4]mi3/4UH|s3/4 , Aq{-EO3FHC |pI5-4(c)OU(c)u|p|o] mi3/4UH|s3/4C |i A PS2 0 0 0 2~0 PS2~PS0 0 1 1 1 1 3 PSA PS1 0 0 1 1 0 0 1 1 PS0 0 1 0 1 0 1 0 1 y-z TMR0rate 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256 WDT rate 1:1 1:2 1:4 1:8 1:16 1:32 1:64 1:128
PSA: wAAW3/4At|i 1: Ati WDT wAAW3/4 0: Ati TMR0 wAAW3/4 EDGE0: TMR *1/2HAaui|i 0 4 EDGE0 1: ~(R)EAAHqq-iCq-(R)E , -p(R)E3/4[ 1C 0: ~(R)EAAHNCq-iq-(R)E , -p(R)E3/4[ 1C SUR0 TMR0 (R)EAA*1/2|i : 5 SUR0 1: ~(R)EAAeJ 0: ((R)EAA )/4 (c)IuO(c)PA I5-4 i3/4UH|s3/4
C. I/OiH|s3/4P i3/4UH|s3/4U|u ]Ou1/4gH|s3/4 ]m@-O , C I/Of@eJ UAe , |Vi|i*O@ , |P1/4E|asNieXCo|oe|Vi|iiI/OiH|s3/4uO@eJ I (c)IeXaeW|aQ1/2s{C|pGH|s3/4Q1/2s{ , (c)O|I/OfNAOueJ1/4O|C
Rev:1.0 Page:8/8
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TM58P05
l {C-p1/4AE3/4O 11 |iGii-p1/4AE3/4 ooU , F|bU- , C-OuO(c)PA 1 , -p1/4AE3/4[ C 1 call, goto, lcall P lgoto: 1/4O|a}(c)ni{CO1/4AE3/4 2. , retla ret iIIW1/4he(R)AE1/4ui{CO1/4AE3/4 P reti: *i{C-p1/4AE3/4iU@-(R)E|UE[ 1 C FiO{C_Ao(c)E , A1/4O|N 2-OuOq(c)ol{C1/2OI(c)MAB , LCALL, Y LGOTO C LCALL (c)M LGOTO iM} o|o|a} ROM , |y](c)w-i|iC CALL GOTO (c)M 3/4@1/4AEAOO , 8 |i(c)M |]|Y-nS(R)i|i 9 |i ( Y-i|i ) M}3/4a-O|sAx3/4C (c)M M|O LCALL LGOTO 1 1 | |i(c)o(c)oM} ROM (c)O|A3/4@1/4AEC l TMRO 08 |iGii-p1/4AE3/4 / -p(R)E3/4AOH|s3/4qL EXT_CLK }~HAau AUAE(c)I uO(c)PA[ 1 C|a||pUS(c)E : A. iAi1/4g
B. 2-O(R)EAA|PB C. iqL]mi3/4UH|s3/4IIi1/2s{wAAW3/4 , aLOO(c)u|bU@*|| -zC l AH|s3/4]t-i|i , W(R)E|i , 1/4q|i(c)M ALU AC -Eo*NO TO (c)MPD Ouwo i, |O*|Q{CiAUC
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Rev:1.0 Page:9/9
TM58P05
|i
A
y-z i|i|iP-E|i|i : [uO iuO 1: L-E|i(Note1) 0: qMSB-E|i ||ii|i|iP||i-E|i|i
0
C 1: q MSBi|i 0: Li|i
1
DC
[uO 1: qC||ii|i 0: LC||ii|i
iuO 1: LC||i-E|i 0: qC||i-E|i
2
Z
01/4x|i: 1: Ae3/4@GO 0 0: Ae3/4@GD 0 ( ) 2 1/4q1/4x|i: 1: Wqa(c)Io|ae LRWDT C uOa G , 1 0: o|aeSLEEP uOa G , 0 *X1/4x|i: 1: Wqa(c)Io|ae CLRWDT(c)ISLEEPuOa G , 1 0: WDT (R)E*X(R)E, G 0 I 5-5 AH|s3/4
3
PD
4
TO
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Rev:1.0 Page:10/10
TM58P05
1: iuOo|aeOqLPi1/4AEGiiE1/2XU[Oe{ , C = 1 NiGO1/4AEC C|iP -E|iAoY|pI 5-5-1(c)OUC B0H50H C B7 B6 B5 B4 B3 B2 B1 B0 1 I x 1 10 011 011 110 000 000 000 0 0 0 I x 0 50HB0H C B7 B6 B5 B4 B3 B2 B1 B0 0 0 1 1 1 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0
I 5-5-1
2: TO (c)MPD |iOC|(R)A BIOPO , _|i|P-i|]C I 5-5-2 A|O(c)uF|P_|i|Z TO (c)MPD -EC
TO 0 0 1 1 AU
PD 0 1 0 1 AU
_|iG qIv1/4O|eoW(R)E q@e1/4O|WDT W(R)E Wq_|i qIv1/4O| MCLR _|i q@e1/4O|MCLR _|i I 5-5-2
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Rev:1.0 Page:11/11
TM58P05
bank i3/4UH|s3/4o|PM}H|s3/4|aM}1/4AE3/4U|sAx3/4 C1/2M}*(R)U3/4U banki3/4UH |s3/4|su bank0 ~ bank1,|]|b@e1/4O|Uu| 5 |i|a}3/4@1/4AEC Banki3/4UH|s3/4 bit5 Q IOi3/4Uu(c)w|sAx3/4 bankC |a} 20H~2FH Oi|su , oC|a}NMi 00H~0FH (Bank0), |a}M|pI 5-6 (c)OU :
1/2M}1/4O| FSR Operand 0 5 I 4
M}1/4O| FSR 54 0
00
0F 10 Select location 1F Select bank Bank 0 0
20~2F are unimplemented, these locations will mapping to 00~0F 30 Select location 3F Bank1 1 Select bank
I 5-6 1/2M}PM}M
l
Port Oi1/2s{ -Eo*NO A~C I/O fC , YI }OeX1/4O| I/O , I/O A uO]AO A }C_|i(R)E(c)O| I/O , I/O }Qm|eJ1/4O| , 1/2iH|s3/4QiAUC IO
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Rev:1.0 Page:12/12
TM58P05
|bA1/4O|NFA_1/2D eKso\a(c)MAEFM}1/4O|CAXR1/4AE3/4U|sAx3/4 , ~, AU 1/4W[F3 -OauA_1/2D(c)Mso\aH|s3/4C o@NoC1/4W[iH|s3/4(c)M|rA S(c)ECA1/4O|1/4AE3/4U|sAx3/4M(c)MM}M|p (c)MI 5-8 (c)OU: I 5-7 A1/4O| T y p e = 1 ) ( 00~1F 00h 01h 02h 03h 04h 05h 06h IAR TMR0 PC STATUS FSR PORTA PORTB General Purpose Register 07-0F General Purpose Register 10-1F I 5-7 A1/4O|1/4AE3/4U|sAx3/4M 1/2M}1/4O| Operand 5 0 00 20 21 22 Unimplemented u 28 M}1/4O| FSR 5 0 General Purpose Register 28-2F Unimplemented 20~3F WAKE_UP IRQM IRQF
17+16=33
Unimplemented
07 08 Location select 1F
Select location 3F
I 5-8 1/2M}(c)MM}M tenx technology, inc.
Rev:1.0 Page:13/13
TM58P05
|bA1/4O|, U-I1/4W[F8 -OqIH|s3/4 YI 5-7 Ii 28~2FC A_1/2D(c)Meoi , H|s3/4 (WAKE_UP, IRQM, IRQF ) AOQAti20, 21, 22 |b@e1/4O|FSR C , <5> Obanki3/4U|i, IOi3/4U bank (0=bank0, 1=bank1)bank1C16 |iMibank0 |bA1/4O|, TM58P05 C C \ 7 |i3/4@1/4AEXYAH3/4/|sAx3/43/4@1/4AE 4:0> , < i1/2M} 00~3F,Y-n banki3/4U|i, iO1/2s{ _Ao(c)EC
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Rev:1.0 Page:14/14
TM58P05
l
eoiH|s3/4 QI@](c)w \(c)ITi ( WAKE_UP ) watchdog , IO~eoH(c)M 1/2DC , _|i(R)E (c)O||iMsC eoH|s3/4aAe(c)wq|pI 5-(c)OU 9 : |i A y-z
7
WDTS
Watch Dog -p(R)E3/4noi|i : TM58P05 DT | W i|i 2 -O (WDTE, WDTS), configuration w O|bWDTE Nwo]m , WDTS |O O|biH|s3/4Nno]m WDT Q]m|Z E , WDTS ~O|(R)A , , ]NO nDTS WDTE W |o AuyAC 1: \ 0: Ti eo\|i : 0: au~eo 1: \~eo\a
6
WUE
5 4
~A_i3/4U : ( 3) EIS 1:PA m 0 @~A_1/2D} 0 m A as-a : P 0 bi directional I/O ----
pin
Af it3 ~1 b W(c)O : 0: Ti~eo 3~1 3 PUH~PUH 1 1: (WUE) & (PUH |pG N |b A ) &N P( eJ@-OU-uH ), oNqI vAeoauC 1|y*Ou@-PC NiHO 2 , 3, (c)I Af 0 : bit W(c)O 0: Ti~eo(c)M~A_ 1: (WUE) & (PUH |pG 0 |b A ) &0 P eJ@-OU-uH ( ) oNqI , vAeoauC (c)II|pGPUH& |b A (EIS) 0 & 0 ) ( eJ@-OU- P( uH ) oI@-OA_1/2DC , . : |pG PUH0, WUE , EIS Qm| `1', oPA0 Q(c)wq|A_1/2De
J}C Figure 5 The Scheme of Wake_Up Register -9 3: A_1/2D*|b@e1/4O|Uo|aeC |pG|bIvAX{A_1/2D, o1/2iauQ~ eoHeo(R)EA_1/2D~*|o|aeCaLeoe|]t (1) Wq_|i (2) ~_|i (3)
0
PUH 0
WDT *X (\(R)E )C |bW|CAU , A_1/2DAOQ(c)C tenx technology, inc.
Rev:1.0 Page:15/15
TM58P05
l
A_I1/2H|s3/4(c)MA_1/4xH|s3/4QI@iA_1/2DB TM58P05 TMR au 0 (c)M~ A_ , |y\A_O(R)MC A_I1/2H|s3/4(c)MA_1/4xH|s3/4a Fig (c)M - (c)OU - 5 Fig 5 : 10 11 |i A y-z 3/4aAe\|i : I M EXINTM NT n (c)M TMR0M |oAuyAC 1: \ 0: Ti RETI uONm INTM `1'C 6~3 ---~A_\: 1:\A_ 0: TiA_
7
INTM
2 1
EXINTM ---TMR0M
~A_\: 1:\A_ 0: TiA_ I 5-10 A_I1/2H|s3/4
|i 7~3 2 1 0
A ---EXINTF ---TMR0F
y-z
~A_1/4x: 1: ~f (PA) ( I~A_1/2DC 0 4)
~A_1/4x: 1: TMR -p1/4AE3/4*XI@-OA_1/2DC 0 I 5-11 A_1/4xH|s3/4
4: A_1/4xONwo]m nouaM1/4xC1/4g 1 i1/4xOLIC ,
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Rev:1.0 Page:16/16
TM58P05
6. \ay-z 6.1 T M R 0 W a t c h d o g -p(R)E3/4 (c)M I 6-1 AaU TMR0 /WDT wAAW3/4e(R)OIC|pI(c)OU, wAAW3/4H|s3/4iHOTMR0 wA AW3/4(c)IOWDT |ZAAW3/4C
Instruction Cycle
EDGE0
Ext_CLK
SUR 0
0
1
2 To 1 MUX
WDT Timer
0 1 0
1
2 to 1 MUX PSA PSA
2 To 1 MUX
8-bit prescaler Synchronize with 2 internal cycles ( T2 and T4 )
8 bit
8 To 1 MUX PS 2~PS 0 TMR0 Counter
1 8 bit 0
2 To 1 MUX PSA
Data bus
WDT time-out
I 6-1 TMR/WDTwAAW3/4e(R)OI 0
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Rev:1.0 Page:17/17
TM58P05
TMR0 O@-O |i-p(R)E3/4/-p1/4AE3/4C 8 TMR0 (R)EAA*1/2iHO|UuO(R)EAA(c)I~(R)EAAC A. i3/4UuO(R)EAA i3/4UH|s3/4SUR0 |iAOMsC*i1/4IIwAAW3/4(R)E ,
-OuO(c)PA[
, TMR0 N*||bC
1C
B.
i3/4U~(R)EAA, i3/4UH|s3/4SUR 0|iAOm1C|bO1/4O| TMR0 , (R)U3/4U EDGE 0OM (c)w|b~ (R)EAAWEu(c)IU-u[C *i TMR0 1 i3/4U~(R)EAA(R)E, A*i*N~(R)EAANP(R)E AAi|ae|PBC TM58P05 qL(R)EAA T2 (c)MT4 o1/4EO|PB~(R)EAAC|pG~1/2A p(c)o 2 -O(R)EAA(c)PA, o1/2Aia*|Q(c)C ]NO ~(R)EAA*|UO|b 2 -O , (R)EAA(c)PAOuA-(c)wAC
WDT -p1/4AE3/4O@-O |iGii-p1/4AE3/4, WDT (R)EAA*1/2ON@-OWY-no|o~(R)EAA 8 RC(R)AuauNC |]|YIauwiJIvA WDT NA~Ao-p1/4AEC-YWDT W(R)E t , IN-OEANW(R)E1/4x|i (AH|s3/4bit4) M0C WDTW(R)E(R)E*|AH*Ax q*1/2qA , AUAE|OAUAE, ABiqL]mwAAW3/4OiAUW(R)E(R)EC qL]mPS~PS 2 0"111 IjAAW ", viF 1:128 C qL PSA|iwAAW3/4iAtiTMR0 WDT WDT(c)I TMR0 (c)I C a|P(R)EIIwAAW3/4C*iw AAW3/4QAti WDT, "CLRWDT "SLEEPuON*|MwAAW3/4(c)M C *iwAAW3/4Q "(c)M " WDT Ati TMR0 o|o1/4gi TMR0 , uO*|MwAAW3/4C
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Rev:1.0 Page:18/18
TM58P05
6.2
_|i
*iU|Co*N@-Ooo ia_|i TM58P05 : (1) Wq (2) 1/4q1/2uoOA@ electrical , refer to character characteristic . (3) RESETB }eJ@-O-t1/2A /VPP (4) WDTW(R)E_|i (|pG\ ).
Power On Power Down (Low Voltage Detector) RESETB/VPP Pin
Power
Oscillator (RC or Crystal)
Synchronize by ripple cpunter
Delay for Setup Time WDTE WDT WDT overflow On-chip RC oscillator Figure 6 S -2 cheme the Reset Controller of
Reset
|pI6-2(c)OU, |-O_|iooQ|CXC 1/4q*|3/4E-PTM58P05 _|i, q-O(R)U3/4U configuration wordbit6~bit5 (c)wqC|bqAooU1/4q_|iiOA@auC|bq(R)S(c)E , (c)wqF 1/4qqA1/2doC|~, 1/4qqA1/2do]uprocess (c)M*AxAUAE1/4vATC@eO , U-IU eaO_|ipN_|iCN_|i(R)Ei(c)oCtO(c)M RC(R)Au3/4OiaOuF, |-IY -nnOE(R)Eoo|h(R)ECF1/2TOtI 1/4q_|i(R)EAPtI(R)EAA|PBCW-Q , 1/2xFpower onncrystal O1/4vAT, |pG power ontvDC,h|ia1/4vAT configuration word Au. : OE(R)Eju 20ms, OE(R)EAHq*1/2qA process *AxAUAE|OAUAEC|ZaIupQU , , 1/4o_|iC |P_|iiH|s3/4(c)M 1/4vAT] O|PC (c)M |iIOM(c)w_|iA ram TO TD (N*Ofigure 5-5-2)CFigure 6 |CXF|P_|i|ZH|s3/4(c)MqI -3 ram-EC
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Rev:1.0 Page:19/19
TM58P05
Address N/A N/A N/A 00h 01h 02h 03h 04h 05h 06h 07h 20h 21h 22h
Name Accumulator IODIR Select IAR TMR 0 PC STATUS BSR PORTA PORTB PORTC WAKE_UP IRQM IRQF General Purpose RAM
Cold Reset xxxx xxxx 1111 1111 111 1111 1 ---- ---xxxx xxxx 111 1111 1111 0001 1xxx -xxx xxxx 0000 xxxx xxxx xxxx xxxx xxxx 0000 0000 0000 0000 0000 0000 Xxxx xxxx
Warm Reset pppp pppp 1111 1111 1111 1111 ---- ---pppp pppp 111 1111 1111 1 000? ?ppp -ppp pppp 0000 pppp pppp pppp pppp pppp 0000 0000 2 0000 0000 0000 0000 Pppp pppp
I 6-3 |sAx3/4i(c)lAE-EK-n X: 1/43/4(c)IL(c)Ox; P: -iO1/4AE-E; ?: I3/4U|P_|ioo
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TM58P05
7. Instruction Set Mnemonic Operands ADD M, m AM ADDAM M, a AND M, m AM ANDAM M, a ANDLA I BC M b0 M, BC M b1 M, BC M b2 M, BC M,b3 M BC M b4 M, BC M b5 M, BC M b6 M, BC M b7 M, BSMM b0 , BSMM b1 , BSMM b2 , BSMM b3 , BSMM b4 , BSMM b5 , BSMM b6 , BSMM b7 , BT SCM b0 M , BT SCM b1 M , BT SCM b2 M , BT SCM b3 M , BT SCM b4 M , BT SCM b5 M , BT SCM b6 M ,
Instruction C o d e A d v a n c)e ( (M)+(acc) (M) / (M)+(acc) (acc) / (M) D / (M) (acc) (M) D / (acc) (acc) Literal (acc)/ (acc) D Clear bit0 of (M) Clear bit1 of (M) Clear bit2 of (M) Clear bit3 of (M) Clear bit4 of (M) Clear bit5 of (M) Clear of (M) bit6 Clear bit7 of (M) Set bit0 of (M) Set bit1 of (M) Set bit2 of (M) Set bit3 of (M) Set bit4 of (M) Set bit5 of (M) Set bit6 of (M) Set bit7 of (M)
Cycles 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Status Affected
OP-code
C, DC, Z 1001011MMM MMMM C, DC, Z 100101 MMM MMMM 0 Z Z Z None None None None None None None None None None None None None None None None 1001001MMM MMMM 100100 MMM MMMM 0 111001 iiii iiii 001100 0MMM MMMM 001100 1MMM MMMM 001101 0MMM MMMM 001101 1MMM MMMM 001110 0MMM MMMM 001110 1MMM MMMM 001111 0MMM MMMM 001111 1MMM MMMM 001000 0MMM MMMM 001000 1MMM MMMM 001001 0MMM MMMM 001001 1MMM MMMM 001010 0MMM MMMM 001010 1MMM MMMM 001011 0MMM MMMM 001011 1MMM MMMM 000100 0MMM MMMM 000100 1MMM MMMM 000101 0MM MMMM M 000101 1MMM MMMM 000110 0MMM MMMM 000110 1MMM MMMM 000111 0MMM MMMM
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If bit0 of (M) = 0, skip next instruction(skip) None 1+ If bit1 of (M) = 0, skip next instruction(skip) None 1+ If bit2 of (M) = 0, skip next instruction(skip) None 1+ If bit3 of (M) = 0, skip next instruction(skip) None 1+ If bit4 of (M) = 0, skip next instruction(skip) None 1+ If bit5 of (M) = 0, skip next instruction(skip) None 1+ If bit6 of (M) = 0, skip next instruction(skip) None 1+
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TM58P05
BT MSCM, b7 BT MSS b0 M, BT MSS b1 M, BT MSS b2 M, BT MSS b3 M, BT MSS b4 M, BT MSS b5 M, BT MSS b6 M, BT MSS b7 M, CALL I CLR A CLR M M CLRWDT COM M, m M COMM M, a DEC M, m M DECM M, a DEC M, m MSZ DEC MSZ M, a GOTO I INC M, m M INCM M, a INC MSZM, m INCMSZ M, a IODIR M IOR M, m AM IORAM M, a IOR l LA If bit7 of (M) = 0, skip next instruction (skip) None 1+ If bit0 of (M) = 1, skip next instruction ( kip) 1+ s None 000111 1MMM MMMM 000000 0MMM MMMM 000000 1MMM MMMM 000001 0MMM MMMM 000001 1MMM MMMM 000010 0MMM MMMM 000010 1MMM MMMM 000011 0MMM MMMM 000011 1MMM MMMM 110110 iiii iiii 100001 0000 0000 100001 MMM MMMM 1 100000 0000 0001 100010 1MMM MMMM 100010 0MMM MMMM 100110 1MMM MMMM 100110 MMM MMMM 0 100111 1MMM MMMM 100111 MMM MMMM 0 11101i iiii iiii 101000 1MMM MMMM 101000 0MMM MMMM 101001 1MMM MMMM 101001 0MMM MMMM 100000 0000 0 MMM 101111 MMM MMMM 1 101111 MMM MMMM 0 110011 iiii iiii
If bit1 of (M) = 1, skip next instruction (skip) None 1+ If bit2 of (M) = 1, skip next instruction (skip) None 1+ If bit3 of (M) = 1, skip next instru 1 + (skip) None ction If bit4 of (M) = 1, skip next instruction (skip) None 1+ If bit5 of (M) = 1, skip next instruction (skip) None 1+ If bit6 of (M) = 1, skip instruction 1 + (skip) None next If bit7 of (M) = 1, skip next instruction (skip) None 1+ Call subroutine Clear accumulator Clear memory M Clear watch register -dog ~(M) / (M) ~(M) / (acc) Decrement M to M (M)- 1 / (acc) (M)- 1 / (M), skip if (M) = 0 (M)- 1 / (acc), skip if (M) = 0 Goto branch (M) + 1 (M) / (M) + 1 (acc) / (M) + 1 (M), skip if (M 0 / )= (M) + 1 (acc), skip if (M) = 0 / Set i/o direction (M) ior (acc) (M) / (M) ior (acc) (a / cc) Literal ior (acc) (acc) / 2 1 1 1 1 1 1 1 None Z Z TO, PO Z Z Z Z
1 + (skip) None 1 + (skip) None 2 1 1 None Z Z
1 + (skip) None 1 + (skip) None 1 1 1 1 None Z Z Z
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TM58P05
LCALL I LGOTO I MOV m AM MOV l LA MOV M, m M MOVM M, a NOP RET RETI RET l LA RL M, m M RLM M, a RR M, m M RRM M, a SELECT SLEEP SUB M, m AM
SUBAM M, a SWAP M, m M SWAPM M, a XORAM M, m XORAM M, a XORLA l
Call subroutine. However, LCALL can 2 addressing 2K address Go branch to any address Move datam acc to memory for Move literalaccumulator to (M) / (M) (M) / (acc) No operation Return Return and enable INTM Return and move literal to accumulator Rotate left from m to itself Rotate left from m to acc Rotate right from m to itself Rotate right from m to acc Set select register Enter sleep (saving) mode (M) -(acc) / (M)
(M) -(acc) / (acc) Swap data from m to itself Swap data from m to acc (M) xor (acc)/ (M) (M) xor (acc)/ (acc) Literal xor (acc) (acc) /
None None None None Z Z None None None None C C C C None TO, PO
C, DC, Z C, DC, Z None None Z Z Z
010iii iiii iiii 011iii iiii iiii 100000 MMM MMMM 1 110001 iiii iiii 100011 1MMM MMMM 10 0011 0MMM MMMM 100000 0000 0000 111111 0111 1111 111111 1111 1111 111100 iiii iiii 101100 1MMM MMMM 101100 0MMM MMMM 101110 1MMM MMMM 101110 0MMM MMMM 100000 0000 0010 100000 0000 0011
10 10101MMM MMMM 10 1010 0 MMM MMMM 10 11011MMM MMMM 10 11010MMM MMMM 10 1011 1 MMM MMMM 10 1011 0 MMM MMMM 11 1000 iiii iiii
2 1 1 1 1 1 2 2 2 1 1 1 1 1 1
1 1 1 1 1 1 1
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Rev:1.0 Page:23/23
TM58P05
8. Electrical Characteristics
8.1 Absolute Maximum Ratings Supply Voltage .... Vss-0.3V to Vss+5.5V Storge Temperature ....... -50 C to 125 C Input Voltage ...... Vss-0.3V to VDD+0.3V Operating Temperature ....-40 C to 85 C
O O O O
8.2 DC Characteristics
Symbol Parameter VDD Operating Voltage Test Conditions Conditions Min Typ Max Unit
VDD
--Low Voltage Detector
2.5
(Idd = 3uA) Config bit6.bit5=00 Low Voltage Detector
5.5 4
V V
5V
VDVT
Detect Voltage
V 2 V V
3V
(Idd = 1.5uA) Config bit6.bit5=10
VIH VIL IDD1 IIL
Input High Voltage Input Low Voltage
5V 5V 5V 5V
I/O Port I/O Port LVD disable, WDT disable LVD disable, WDT enable Vin=VDD, VSS Voh=4.5V
2
VDD 0.8 1 10 1 9 17 23 20 35 50
Standby Current Input Leakage Current I/O Port Driving Current
uA uA
IOH
5V
Voh=4V Voh=3.5V Vol=0.5V
mA
IOL
I/O Port Sink Current
5V
Vol=01V Vol=1.5V
mA
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Rev:1.0 Page:24/24
TM58P05
8.3 AC Characteristics
Test Conditions Symbol Parameter VDD 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V Conditions LS Crystal mode NS Crys tal mode HS Crystal mode RC mode 20 20 6 6 mS mS Mhz Min 32 32 1 1 10 Typ Max 200 200 10 10 20 Khz Mhz Unit Khz
fsys1 fsys1 fsys3 fsys4 Tw d t Tr h t
System Clock System Clock System Clock System Clock Watchdog Timer Reset Hold Time
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Rev:1.0 Page:25/25

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